Embodiments of the present invention disclosed herein relate to a semiconductor memory device, and more particularly, to a nonvolatile memory device and a method of forming the same.
In general, a semiconductor manufacturing process includes a process of forming a desired pattern by removing any unnecessary portions of a layer through a photolithographic patterning process after forming various types of layers on a substrate. A conductive pattern so formed, for example, may take the form of a line-type pattern such as a gate which extends in a predetermined direction, or an island-like conductive pattern such as a bottom electrode of a capacitor. In order to embody a highly integrated device, it is inevitably desired to reduce the width of the conductive pattern, and to shorten the distance between the adjacent conductive patterns. Such reduction of the width of the conductive pattern, however, causes the resistance of the conductive pattern to be increased, and thus, to maintain a lower resistance, it is necessary to form the conductive pattern as thick as possible. In order to form a conductive pattern of increased thickness, an etching process should be performed using a photoresist pattern after forming a thick conductive layer. However, if the conductive layer is too thick, it is difficult to form the conductive pattern with a desired sidewall profile because the photoresist pattern can become somewhat abraded during the etching process. Therefore, to overcome this problem, the thick conductive layer is patterned using a hard mask layer which is harder than the photoresist, wherein the hard mask layer is formed of a nitride layer, an oxide layer or a combination thereof. Due to this hard mask layer, however, the conductive pattern becomes physically higher than the case of using the photoresist pattern.
Accordingly, as the device becomes more highly integrated, the distance between the adjacent conductive patterns becomes further reduced, whereas the thickness of each conductive pattern is further increased. As a result, the region between the adjacent patterns has a small width and a large height. That is, the region has high aspect ratio.
Meanwhile, an interlayer insulating layer is commonly filled into the region between the adjacent conductive patterns for insulating the adjacent conductive patterns from each other. However, since this region has a high aspect ratio as described above, it is difficult to fill the interlayer insulating layer into this region sufficiently so that there may exist a void in the interlayer insulating layer. When a void is present in the interlayer insulating layer, the adjacent conductive patterns can become electrically connected to each other when later performing a contact-forming process of patterning the interlayer insulating layer and depositing conductive material thereon. Accordingly, it is difficult to secure device reliability.
Therefore, it becomes necessary to remove the hard mask used in forming the conductive pattern. Particularly, in manufacturing a nonvolatile memory device in which a memory cell has a stacked gate structure, it is essential to be able to remove the hard mask through a relatively simple process because the thickness of the layer to be patterned is too great and the region between the adjacent stacked gate structures has a high aspect ratio.